NDLI: Concurrent testing of digital circuits for advanced fault models

Content Provider	IEEE Xplore Digital Library
Author	Biswas, S. Mukhopadhyay, S. Patra, A. Sarkar, D.
Copyright Year	2006
Description	Author affiliation: Adv. VLSI Design Lab., IIT Kharagpur (Biswas, S.; Mukhopadhyay, S.; Patra, A.; Sarkar, D.)
Abstract	This work is concerned with the development of generic, non-intrusive and flexible algorithms for the design of digital circuits with on line testing (OLT) capability. Most of the works presented in the literature on OLT have used single stuck at fault models. However, in deep sub micron era single s-a fault models may not capture more than a fraction of the real defects. To cater to the problem it is now advocated that additional fault models such as resistive bridging faults, transition faults, delay faults etc. are also used. The proposed technique is one of the first works that enables on-line detection of resistive bridging faults and provides a high value of n for the n-detect tests. The technique can handle generic digital circuits with cell count as high as 15,000 and having the order of $2^{500}$ states. Results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal increase in area overhead, if compared to ones with single s-a fault coverage, the proposed scheme also provides coverage for resistive bridging faults and high value of n for n-detect coverage. The results have also been verified in silicon using FPGAs
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	202
Ending Page	207
File Size	228994
Page Count	6
File Format	PDF
ISBN	1424401852
DOI	10.1109/DDECS.2006.1649612
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-18
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Digital circuits Circuit faults Algorithm design and analysis Delay Electrical fault detection Fault detection Detectors Benchmark testing Silicon
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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