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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chaogeng Huang Hong Xu Yanhong Chen Yixiao Li Tao Hong |
| Copyright Year | 2014 |
| Description | Author affiliation: Sch. of Inf., Zhejiang Univ. of Finance & Econ., Hangzhou, China (Chaogeng Huang; Yanhong Chen; Yixiao Li) || Coll. of Inf. Eng., Zhejiang Univ. of Technol., Hangzhou, China (Hong Xu; Tao Hong) |
| Abstract | In this paper, a pipelined implementation of a Hessenberg-based input balanced realization is derived, which is realized by placing the delay elements in the lower path and the upper path alternately. The proposed pipelined structure is canonical in the sense that no extra delay is needed. For an Nth order filter, the proposed structure requires 5N -1 multipliers, which has two less multipliers than the normalized lattice structure. Two numerical examples are presented to demonstrate the performance of the proposed structure comparing with the other traditional structures. |
| Starting Page | 488 |
| Ending Page | 492 |
| File Size | 278722 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9781479943159 |
| DOI | 10.1109/ICIEA.2014.6931213 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-06-09 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delays Transfer functions Lattices Noise Educational institutions Pipeline processing Sensitivity state-space realization Digital filter structures pipelining finite word length |
| Content Type | Text |
| Resource Type | Article |
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