NDLI: An FPGA configuration circuit based on JTAG

Content Provider	IEEE Xplore Digital Library
Author	Huiguo Zhang Yulan Tang Zongguang Yu
Copyright Year	2009
Description	Author affiliation: No. 58 Research Institute, China Electronics Technology Group Corporation, Wuxi, Jiangsu 214000, China (Zongguang Yu) \|\| School of Information Engineering, Jiangnan University, Wuxi, Jiangsu 214000, China (Huiguo Zhang; Yulan Tang)
Abstract	An FPGA configuration circuit based on JTAG is designed. The configuration circuit has the JTAG architecture which is compatible with the IEEE standard 1149.1. Under the shift function of JTAG, a data chain for configuration is provided. The process of the configuration is controlled by three simple counters. Implemented with the CSMC 0.5um technology, the configuration circuit has the area of $1.404mm^{2},$ occupies the 3 percent of total FPGA area. Compared with the control scheme of complex state machine, this design is simple and has been used in an FPGA.
Starting Page	2588
Ending Page	2590
File Size	453698
Page Count	3
File Format	PDF
ISBN	9781424427994
DOI	10.1109/ICIEA.2009.5138675
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Logic testing Circuit testing Integrated circuit interconnections Electronic equipment testing Logic arrays Pins Clocks Counting circuits Automata CRC FPGA Configuration circuit JTAG
Content Type	Text
Resource Type	Article

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