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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chin-Long Wey Shin-Yo Lin |
| Copyright Year | 2007 |
| Description | Author affiliation: Nat. Central Univ. Jhong-li, Taoyuan (Chin-Long Wey; Shin-Yo Lin) |
| Abstract | The residue number system (RNS) provides an attractive alternative to traditional weighted number systems for high speed digital signal processing (DSP) and communication applications. To interface with the digital system, where the binary numbers are employed, the RNS-based processors require the conversions between binary form to the residue representation. This paper presents a simple conversion algorithm and hardware implementation for any arbitrary moduli sets $\{2^{kn}$ $,2^{n}-1,2^{n}+1\},$ where k is a positive integer. The converter hardware includes nothing but (2n) converting units, where each unit is comprised of a 1-bit FA (full adder), a 2-to-1 MUX (multiplexer), and two latches. Experimental results show that, for n=6 and k=2, the converter takes only an area of 16,968 um with a delay of 14.20 ns, and, for n=8 and k=4, the area is 22,624 $um^{2}$ with a delay of 19.54 ns, where the TSMC 0.18 um 1P6M process were employed. Both area and speed performances are significant. |
| Starting Page | 536 |
| Ending Page | 541 |
| File Size | 782251 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424409402 |
| DOI | 10.1109/EIT.2007.4374470 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-17 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Digital signal processing Delay Hardware Digital systems Signal processing algorithms Multiplexing Portable computers Circuits Adders |
| Content Type | Text |
| Resource Type | Article |
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