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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Onkaraiah, S. Reyboz, M. Clermidy, F. Portal, J. Bocquet, M. Muller, C. Hraziia, H. Anghel, C. Amara, A. |
| Copyright Year | 2012 |
| Description | Author affiliation: IM2NP, UMR CNRS 6242, Aix-Marseille Université, Marseille, France (Portal, J.; Bocquet, M.; Muller, C.) || CEA-LETI MINATEC, Grenoble, France (Onkaraiah, S.; Reyboz, M.; Clermidy, F.) || ISEP, Paris, France (Hraziia, H.; Anghel, C.; Amara, A.) |
| Abstract | Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ∼3.2µW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future “Power-on, Power-off” application adding Non-Volatility without significant burdening of the existing architectures. |
| Starting Page | 417 |
| Ending Page | 420 |
| File Size | 1004199 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467308571 |
| e-ISBN | 9781467308595 |
| e-ISBN | 9781467308588 |
| DOI | 10.1109/NEWCAS.2012.6329045 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-06-17 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Nonvolatile memory Flip-flops Computer architecture Latches Transistors Switches Delay |
| Content Type | Text |
| Resource Type | Article |
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