NDLI: Implementation of Hardware Multithreading in a Pipelined Processor

Content Provider	IEEE Xplore Digital Library
Author	Manjikian, N.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Queen's Univ., Kingston, Ont. (Manjikian, N.)
Abstract	This paper outlines requirements for introducing hardware support for multithreading in a pipelined 32-bit processor that has been used for prototyping single-chip multiprocessor implementations in programmable logic. The inclusion of multithreading within a processor complements the use of multiple processor instances by enabling multiple execution contexts to share a single processor with fast hardware-supported context switching, in addition to having multiple contexts executing in parallel on distinct processors. New instructions for thread management are described, and modifications to the existing processor for supporting up to eight threads are outlined. Synthesis results obtained using Altera Quartus II for a Stratix logic chip indicate an overhead of 21% for multithreading in terms of logic elements, with the largest contribution from multiple program counters and the associated logic to multiplex their outputs and set their contents. There is no additional overhead related to embedded memory blocks because previously-unused storage is allocated to distinct register files for multiple threads. From the initial experience of developing enhancements for multithreading, future work will refine the support for multithreading and apply this capability in multiprocessor implementations
Sponsorship	IEEE CAS
Starting Page	145
Ending Page	148
File Size	97559
Page Count	4
File Format	PDF
ISBN	1424404169
DOI	10.1109/NEWCAS.2006.250918
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-18
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Multithreading Yarn Counting circuits Programmable logic arrays Programmable logic devices Intellectual property Registers Hazards Prototypes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design issues for prototype implementation of a pipelined superscalar processor in programmable logic

Performance enhancement and high-level specification of a pipelined processor in programmable logic

Cooperative multithreading in dynamically reconfigurable systems

High Perfomance Multitask Processor For Real Time Applications

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

Design and implementation of emulator on FPGA

CMOS implementation of programmable logic gates and pipelined full adders using threshold logic gates based on NDR devices

MT ARM: multithreading implementation in Arm7 architecture

A 16-bit monolithic $I^{3}L$ processor

Implementation of Hardware Multithreading in a Pipelined Processor

Similar Documents

Design issues for prototype implementation of a pipelined superscalar processor in programmable logic

Performance enhancement and high-level specification of a pipelined processor in programmable logic

Cooperative multithreading in dynamically reconfigurable systems

High Perfomance Multitask Processor For Real Time Applications

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

Design and implementation of emulator on FPGA

CMOS implementation of programmable logic gates and pipelined full adders using threshold logic gates based on NDR devices

MT ARM: multithreading implementation in Arm7 architecture

A 16-bit monolithic $I^{3}L$ processor

Implementation of Hardware Multithreading in a Pipelined Processor