NDLI: Low-power high-speed level shifter design for block-level dynamic voltage scaling environment

Content Provider	IEEE Xplore Digital Library
Author	Tran, C.Q. Kawaguchi, H. Sakurai, T.
Copyright Year	2005
Description	Author affiliation: Inst. of Ind. Sci., Tokyo Univ., Japan (Tran, C.Q.; Kawaguchi, H.; Sakurai, T.)
Abstract	Two novel level shifters that are suitable for block-level dynamic voltage scaling environment (namely, V/sub DD/-hopping) are proposed. In order to achieve reduction in power consumption and delay, the first proposed level shifter which is called contention mitigated level shifter (CMLS) uses a contention-reduction technique. The simulation results with 65-nm CMOS model show 24% reduction in power and 50% decrease in delay with 4% area increase compared with the conventional level shifter. The second proposed level shifter which is called bypassing enabled level shifter (BELS) implements a bypass function and it is fabricated using 0.35/spl mu/m CMOS technology. The measurement results show that the power and delay of the proposed BELS are reduced by 50% and 65%, respectively with 60% area overhead over the conventional level shifter.
Sponsorship	IEEE Central Texas Sect. Japan Soc. of Appl. Phys
Starting Page	229
Ending Page	232
File Size	631163
Page Count	4
File Format	PDF
ISBN	0780390814
DOI	10.1109/ICICDT.2005.1502637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dynamic voltage scaling Delay Circuits Energy consumption Voltage control Low voltage Collaboration Semiconductor device modeling CMOS technology Area measurement
Content Type	Text
Resource Type	Article

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