NDLI: Compact and short critical path finite field inverter for cryptographic S-box

Content Provider	IEEE Xplore Digital Library
Author	Wong, M.M. Wong, M.L.D. Zhang, C. Hijazin, I.
Copyright Year	2015
Description	Author affiliation: Fac. of Eng. & Ind. Sci., Swinburne Univ. of Technol., Melbourne, VIC, Australia (Zhang, C.; Hijazin, I.) \|\| Fac. of Eng., Comput. & Sci., Swinburne Univ. of Technol., Kuching, Malaysia (Wong, M.M.; Wong, M.L.D.)
Abstract	A substitution box (S-box) plays a crucial role in symmetric key cryptography with block ciphers, such as those found in the Data Encryption Standard (DES) and the Advanced Encryption Standard (AES). It serves as the predominant component in most block ciphers, of which the computational complexity impacts the security of the ciphers directly. In essence, a S-box performs a non-linear transformation of the input data block through a finite field inversion, which is incidentally the most expensive operation in digital computation of finite field arithmetic. Consequently, its computational cost will also increase the overall hardware requirements and in turn, decrease the overall performance of the ciphers. With the emergence of Internet of Things (IoT), the need for highly secured yet lightweight implementation protocols is becoming increasingly more observable. In this paper, we propose a new finite field inverter over $GF(2^{8})$ with a significant area cost saving, achieved through direct computation and followed by algebraic factorization and common sub-expression elimination (CSE). The proposed inverter could be deployed into AES cipher on highly area-constrained digital platforms.
Starting Page	775
Ending Page	779
File Size	150481
Page Count	5
File Format	PDF
ISSN	21653577
e-ISBN	9781479980581
DOI	10.1109/ICDSP.2015.7251981
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-21
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inverters Logic gates Ciphers Boolean functions Hardware Standards S-box Finite field inversion Algebraic Factorization Common Sub-expression Elimination (CSE) Low complexity
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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