NDLI: Utility-aware Resource Allocation in an Event Processing System

Content Provider	IEEE Xplore Digital Library
Author	Bhola, S. Astley, M. Saccone, R. Ward, M.
Copyright Year	2005
Description	Author affiliation: IBM T. J. Watson Research Center, 19 Skyline Drive, Hawthorne, NY 10532, sbhola@us.ibm.com (Bhola, S.)
Abstract	Event processing systems link event producers and consumers in a flexible manner, by supporting multiple communication patterns and powerful message transformations. Such systems support both loosely coupled communication patterns, such as one-to-one or one-to-many and tightly coupled (request-response) patterns. An important concern in these systems is the allocation of resources used to support event processing. These include traditional constrained resources such as CPU and network, as well as an increasing reliance on storage resources. For instance, transactional and reliable producers require events to be logged to stable storage. In this paper we consider the problem of utility driven allocation of these resources, taking into account resource capacity. In contrast to previous work, we (1) develop a unified utility model to deal with throughput requirements of one-way flows and latency requirements of request-response flows, (2) differentiate between classes of consumers for one-to-many flows and subject these classes to consumer admission control, (3) compute system optimization constraints using both resource bandwidth and latency and (4) develop a control architecture that combines periodic optimization with continuous rate control, both of which are utility aware. We describe an experimental evaluation of our approach on a prototype event processing server.
Starting Page	55
Ending Page	64
File Size	2564630
Page Count	10
File Format	PDF
ISBN	1424401755
DOI	10.1109/ICAC.2006.1662382
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-12
Publisher Place	Ireland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resource management Delay Gold Admission control Constraint optimization Communication system control Filtering Filters Throughput Bandwidth
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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