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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Krukowski, L. Sugier, J. |
| Copyright Year | 2008 |
| Description | Author affiliation: Microtech Int. Ltd. Sp. z o.o, Wroclaw (Krukowski, L.) |
| Abstract | This paper discusses different design options for realization of AES cryptographic algorithm in programmable logic devices and illustrates them with practical results of hardware implementation. The discussion begins with those aspects of the four basic cipher transformations that are essential for realization with resources available in FPGA devices, then moves to various possible organizations of the cipher unit and concludes with efficiency and size comparison of results obtained after implementation of the AES-128 version of the method in Spartan-3 devices from Xilinx. Instead of searching for a "global optimum" specific low-cost FPGA implementation, the paper summarizes main directions of design development that are viable today and evaluates them by a case study example. |
| Starting Page | 347 |
| Ending Page | 354 |
| File Size | 315070 |
| Page Count | 8 |
| File Format | |
| ISBN | 9780769531793 |
| DOI | 10.1109/DepCoS-RELCOMEX.2008.36 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-06-26 |
| Publisher Place | Poland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | FPGA device AES algorithm |
| Content Type | Text |
| Resource Type | Article |
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