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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Leo Chin Sim Leedham, G. Schroder, H. |
| Copyright Year | 2002 |
| Description | Author affiliation: Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore (Leo Chin Sim; Leedham, G.) |
| Abstract | This paper describes the performance evaluation of an SIMD system on a commonly encountered standard linear equation problem. We introduce a prototype SIMD system, called the Systola 1024; whose parallel architecture is based upon the instruction systolic array concept. To evaluate the performance of this architecture we have implemented an in-cache problem to measure its MFLOP by solving the Gaussian elimination problem to obtain the LU factorization. We also examine the effects of increasing the array processors by a certain factor. |
| Starting Page | 910 |
| Ending Page | 913 |
| File Size | 314980 |
| Page Count | 4 |
| File Format | |
| ISBN | 9810483643 |
| DOI | 10.1109/ICARCV.2002.1238545 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-12-02 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Nanyang Technological Univ |
| Subject Keyword | Systolic arrays Random access memory Read-write memory Embedded computing High performance computing Computer architecture Application software Biology computing Concurrent computing Computer aided instruction |
| Content Type | Text |
| Resource Type | Article |
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