NDLI: A Parallelization of ECDSA Resistant to Simple Power Analysis Attacks

Content Provider	IEEE Xplore Digital Library
Author	Aravamuthan, S. Thumparthy, V.R.
Copyright Year	2007
Description	Author affiliation: Adv. Technol. Center, Tata Consultancy Services Ltd., Hyderabad, India (Aravamuthan, S.)
Abstract	The Elliptic Curve Digital Signature Algorithm admits a natural parallelization wherein the point multiplication step can be split in two parts and executed in parallel. Further parallelism is achieved by executing a portion of the multiprecision arithmetic operations in parallel with point multiplication. This results in a saving in timing as well as gate count when the two paths are implemented in hardware and software. This article attempts to exploit this parallelism in a typical system context in which a microprocessor is always present though a hardware accelerator is being designed for performance. We discuss some implementation aspects of this design with reference to power analysis attacks. We show how the Montgomery point multiplication and the binary extended gcd algorithms can be adapted to prevent simple power analysis attacks. We implemented our design using a hardware/software parallel architecture. We present the results when the software component is coded on an 8051 architecture and an ARM7TDMI processor. Our enhancements find applications in security environments such as servers, smart cards etc.
Starting Page	1
Ending Page	7
File Size	678044
Page Count	7
File Format	PDF
ISBN	1424406137
DOI	10.1109/COMSWA.2007.382592
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Elliptic curves Digital signatures Arithmetic Timing Microprocessors Algorithm design and analysis Parallel architectures Computer architecture Application software
Content Type	Text
Resource Type	Article

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