NDLI: Improving Network's Performability Using Parallel Processing

Content Provider	IEEE Xplore Digital Library
Author	Zolpirani, M.S. Bidmeshki, M.-M. Miremadi, S.G.
Copyright Year	2007
Description	Author affiliation: Sharif Univ. of Technol., Tehran (Zolpirani, M.S.; Bidmeshki, M.-M.)
Abstract	By occurring failures in computer networks, routing protocols are triggered to update routing and forwarding tables. Because of invalid tables during update-time, transient loop may occur and packet-drop rate and end-to-end delay increase which means that the quality of service decreases. This paper proposes a parallel architecture for a router to recalculate and update routing table. Simulation results show that with dual-processor architecture, this update time could be up to 40% improved, depending on the network topology and the size of tables. This paper also studies the effect of this speed-up on networks' performability, i.e. the ability to deliver services at predefined level. A sample network is studied and the simulation results show that faster updates of routing table, improves network's performability in the presence of failures. Since it may not worth or even be practical to improve all routers in the network, this paper suggests finding bottleneck routers and accelerating them in order to improve the performability of the networks. The simulation results show that by speeding-up the bottleneck routers of the network, instead of all routers, the performability still could be improved.
Starting Page	40
Ending Page	40
File Size	329732
Page Count	1
File Format	PDF
ISBN	0769528058
DOI	10.1109/ICN.2007.48
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-22
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Routing protocols Convergence Web and internet services Computer networks Concurrent computing Delay Quality of service Parallel architectures Network topology Performability Failure Parallel Processing SPF Calculation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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