NDLI: A model inaccuracy aware design methodology of millimeter-wave CMOS tuned amplifiers

Content Provider	IEEE Xplore Digital Library
Author	Shih-Chieh Shin Dawn, D. Yeh, D. Laskar, J.
Copyright Year	2011
Description	Author affiliation: Samsung Electro-Mechanics America, Inc., Atlanta, Georgia, 30308 U.S.A (Yeh, D.) \|\| School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30308 U.S.A (Shih-Chieh Shin; Dawn, D.)
Abstract	This paper presents a systematic design methodology of millimeter wave (mm-wave) CMOS tuned amplifier which, for the first time to the best of authors' knowledge, takes the model inaccuracy at mm-wave frequencies into design consideration. Millimeter-wave models for both passive and active components are developed based on the standard foundry provided models with extra critical variation components which represent modeling uncertainties. The proposed model is verified through a comparison with the measured results of the test structures. The design methodology of tolerating the modeling uncertainties is demonstrated by a design example of a 65nm CMOS 57–64 GHz low noise amplifier, which has a 20 dB gain and a minimum 5 dB noise figure with 26 mA current consumption under 1 V supply.
Starting Page	1
Ending Page	6
File Size	988972
Page Count	6
File Format	PDF
ISBN	9781612840819
e-ISBN	9781612840802
DOI	10.1109/WAMICON.2011.5872876
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Capacitors Transmission line measurements Foundries Power transmission lines Inductors Shunt (electrical) low noise amplifier (LNA) millimeter-wave (mmW) CMOS tuned-amplifier
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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