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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xiao-jing Zhu Hong-bo Zeng Kun Huang Ge Zhang |
| Copyright Year | 2008 |
| Description | Author affiliation: Univ. of Sci. & Technol. of China, Hefei (Xiao-jing Zhu) |
| Abstract | Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of network on chip, which are called rr-path, rr-dist and rr-al respectively, rr-path schedules the NoC traffic according to the distance between the source node and the destination node, and rr-dist schedules the NoC traffic according to the distance between the current and the destination nodes, and rr-al schedules the NoC traffic according to the difference between the arrival and the left flits numbers of every ports. We implement these algorithms in a network simulator, and analyze their performance using hotspot and uniform traffic patterns. Compared to round-robin scheduling algorithm, all of the new algorithms can reduce the max communication latency. In most cases, they can also reduce the average communication latency. Consequently, these new algorithms can improve the performance of multiprocessor systems. |
| Starting Page | 46 |
| Ending Page | 51 |
| File Size | 3353740 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424416851 |
| DOI | 10.1109/ICNSC.2008.4525181 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-04-06 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Scheduling algorithm Network-on-a-chip Telecommunication traffic Traffic control Switches Round robin Processor scheduling Delay Computer networks High performance computing |
| Content Type | Text |
| Resource Type | Article |
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