NDLI: Bounded Dataflow Networks and Latency-Insensitive circuits

Content Provider	IEEE Xplore Digital Library
Author	Vijayaraghavan, Muralidaran Arvind
Copyright Year	2009
Description	Author affiliation: Computation Structures Group, Computer Science and Artificial Intelligence Lab, Massachusetts Institute of Technology, USA (Vijayaraghavan, Muralidaran; Arvind)
Abstract	We present a theory for modular refinement of Synchronous Sequential Circuits (SSMs) using Bounded Dataflow Networks (BDNs). We provide a procedure for implementing any SSM into an LI-BDN, a special class of BDNs with some good compositional properties. We show that the Latency-Insensitive property of LI-BDNs is preserved under parallel and iterative composition of LI-BDNs. Our theory permits one to make arbitrary cuts in an SSM and turn each of the parts into LI-BDNs without affecting the overall functionality. We can further refine each constituent LI-BDN into another LI-BDN which may take different number of cycles to compute. If the constituent LI-BDN is refined correctly we guarantee that the overall behavior would be cycle-accurate with respect to the original SSM. Thus one can replace, say a 3-ported register file in an SSM by a one-ported register file without affecting the correctness of the SSM. We give several examples to show how our theory supports a generalization of previous techniques for Latency-Insensitive refinements of SSMs.
Starting Page	171
Ending Page	180
File Size	1048995
Page Count	10
File Format	PDF
ISBN	9781424448067
DOI	10.1109/MEMCOD.2009.5185393
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Timing Delay Clocks Wire Sequential circuits Registers Computer networks Computer science Artificial intelligence
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA mapping of sequential circuits with retiming

Technology mapping for sequential circuits based on retiming techniques

Bounded dataflow networks and latency-insensitive circuits

Timing Fault Detection in FPGA-Based Circuits

Delay budgeting in sequential circuit with application on FPGA placement

A practical cut-based physical retiming algorithm for field programmable gate arrays

Implementing latency-insensitive dataflow blocks

FLYSIG: dataflow oriented delay-insensitive processor for rapid prototyping of signal processing

Optimal clock period FPGA technology mapping for sequential circuits

Bounded Dataflow Networks and Latency-Insensitive circuits

Similar Documents

FPGA mapping of sequential circuits with retiming

Technology mapping for sequential circuits based on retiming techniques

Bounded dataflow networks and latency-insensitive circuits

Timing Fault Detection in FPGA-Based Circuits

Delay budgeting in sequential circuit with application on FPGA placement

A practical cut-based physical retiming algorithm for field programmable gate arrays

Implementing latency-insensitive dataflow blocks

FLYSIG: dataflow oriented delay-insensitive processor for rapid prototyping of signal processing

Optimal clock period FPGA technology mapping for sequential circuits

Bounded Dataflow Networks and Latency-Insensitive circuits