NDLI: A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study

Content Provider	IEEE Xplore Digital Library
Author	Haynal, S. Kam, T. Kishinevsky, M. Shriver, E. Xinning Wang
Copyright Year	2008
Description	Author affiliation: Strategic CAD Labs., Intel Corp., Hillsboro, OR (Haynal, S.; Kam, T.; Kishinevsky, M.; Shriver, E.; Xinning Wang)
Abstract	This paper presents a new tool for SystemVerilog RTL modifications with on-the-fly validation of local RTL changes. The tool, SV-rewrite, imports an initial version of SystemVerilog RTL and elaborates it into a hierarchical design description visualized as structural diagrams. From the design cockpit the user can select any set of visualized components, open a favorite text editor, modify then validate the new RTL description, and finally substitute this new rewritten RTL into the larger model to replace the originally selected components. This process of local validated rewrites can be repeated until the entire RTL is safely rewritten. We studied RTL abstraction using SV-rewrite to abstract the Pentium 80602 (P54CS) integer execution unit and register file. We have produced a significantly more readable RTL that is 2 to 3 times smaller than the original one. The abstracted RTL was validated by booting Linux on an FPGA-based emulation platform.
Starting Page	79
Ending Page	88
File Size	698814
Page Count	10
File Format	PDF
ISBN	9781424424177
DOI	10.1109/MEMCOD.2008.4547693
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Design automation Visualization Computer bugs Visual databases Linux Emulation Testing Signal generators Signal analysis
Content Type	Text
Resource Type	Article

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