NDLI: Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Content Provider	IEEE Xplore Digital Library
Author	Vasudevan, S. Abraham, J.A. Viswanath, V. Jiajin Tu
Copyright Year	2006
Description	Author affiliation: Comput. Eng. Res. Center, Texas Univ., Austin, TX (Vasudevan, S.; Abraham, J.A.)
Abstract	Sequential equivalence checking between system level descriptions of designs and their register transfer level (RTL) implementations is a very challenging and important problem in the context of systems on a chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in system level languages or hardware description languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a SystemC description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC
Sponsorship	ACM SIGon Design Auto. IEEE Circuits and Syst. Soc. IEEE Comput. Soc. IEEE Council on EDA
Starting Page	71
Ending Page	80
File Size	388068
Page Count	10
File Format	PDF
ISBN	1424404215
DOI	10.1109/MEMCOD.2006.1695903
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Design engineering Design optimization Hardware design languages Flip-flops Jacobian matrices Registers Viterbi algorithm Decoding Timing
Content Type	Text
Resource Type	Article

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