NDLI: Checkers for SystemC designs

Content Provider	IEEE Xplore Digital Library
Author	Grobe, D. Drechsler, R.
Copyright Year	2004
Description	Author affiliation: Inst. of Comput. Sci., Bremen Univ., Germany (Grobe, D.; Drechsler, R.)
Abstract	Today's complex systems are modeled on a high level of abstraction. In this context, C/C++-based description languages, like SystemC, become very important. The modeling features of SystemC enable adequate levels of abstraction, hardware/software integration and fast executable specifications. Using the SystemC design methodology, a system is partitioned into hardware and software. Then the modules are refined down to the implementation. Besides efficient modeling, the correct functional behavior is very important. Already today up to 80% of the overall design costs are due to verification. As the complete system cannot be formally verified, checking of the functional behavior during operation has to be considered. In this paper an approach is presented that allows to check temporal properties for a SystemC design not only during simulation, but also after fabrication inform of an on-line test. The method translates the properties into synthesizable SystemC instructions. By this, the properties can be checked like HDL assertions during simulation and after production since they can be synthesized together with the system. The proposed approach enables a concise circuit and system verification methodology.
Sponsorship	ACM Special Interest Group on Design Autom. IEEE Circuits and Syst. Soc. IEEE Comput. Soc. Design Autom. Tech. Comm. (DATC)
Starting Page	171
Ending Page	178
File Size	1141512
Page Count	8
File Format	PDF
ISBN	0780385098
DOI	10.1109/MEMCOD.2004.1459851
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Circuit synthesis Design methodology Costs Fabrication Circuit testing System testing Hardware design languages Production systems Circuits and systems
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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