NDLI: Performance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs

Content Provider	IEEE Xplore Digital Library
Author	Markovic, N. Nemirovsky, D. Unsal, O.S. Valero, M. Cristal, A.
Copyright Year	2015
Description	Author affiliation: Barcelona Supercomput. Center, Barcelona, Spain (Markovic, N.; Nemirovsky, D.; Unsal, O.S.; Valero, M.; Cristal, A.)
Abstract	As thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. Since more and more applications become multi-threaded we expect to find a growing number of threads executing on a machine. Consequently, the operating system will require increasingly larger amounts of CPU time to schedule these threads efficiently. Instead of perpetuating the trend of performing more complex thread scheduling in the operating system, we propose a hardware implementation of the Thread Lock Section-aware Scheduling (TLSS) scheduling mechanism. This lightweight mechanism helps to identify multi-threaded application bottlenecks such as thread synchronization sections and complements the Fairness-aware Scheduler method. It is, to our knowledge, the first hardware based lock section-aware scheduling that is energy attentive and can be applied to both asymmetric and symmetric CMPs. It achieves an average performance gains of 10.9 percent (geometric mean) compared to the state-of-the-art Linux OS Scheduler when applied on the Symmetrical Chip Multi-Processor (SCMP). At the same time, it is 81 percent more EDP (energy-delay product) efficient when applied on an Asymmetrical Chip Multi-Processor (ACMP) and compared to the Linux OS Scheduler on an SCMP, where ACMP and SCMP take relatively the same chip area.
Starting Page	33
Ending Page	40
File Size	736070
Page Count	8
File Format	PDF
ISBN	9781467380119
ISSN	15506533
DOI	10.1109/SBAC-PAD.2015.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-17
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Instruction sets Hardware Multicore processing Operating systems Job shop scheduling Runtime Energy Efficiency Chip Multiprocessor Hardware Thread scheduling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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