NDLI: Instruction usage and the memory gap problem

Content Provider	IEEE Xplore Digital Library
Author	Fernandes, E.S.T. Barbosa, V.C. Ramos, F.
Copyright Year	2002
Description	Author affiliation: COPPE, Univ. Fed. do Rio de Janeiro, Brazil (Fernandes, E.S.T.; Barbosa, V.C.; Ramos, F.)
Abstract	The gap between memory and processor speeds is responsible for the substantial amount of idle time of current processors. To reduce the impact provoked by the so-called "memory gap problem," many, software techniques (e.g., the code layout reorganization) together with hardware mechanisms (cache memory, translation look-aside buffer branch prediction, speculative execution, trace cache, instruction reuse, and so on) have been successfully implemented. In this paper we present some experiments that explain why these mechanisms and techniques are so efficient. We found that only a small fraction of the object code is actually executed: our experiments disclosed that more than 50% of the instructions remain untouched during the whole execution, and the percentages of basic blocks which remain unused are slightly greater. In addition to the usage of instructions and blocks, the paper provides further insights regarding the behavior of application programs, and gives some suggestions for extra performance gains.
Sponsorship	SBC IFIP - International Federation for Inf. Process. IEEE Comput. Soc
Starting Page	169
Ending Page	175
File Size	438883
Page Count	7
File Format	PDF
ISBN	0769517722
DOI	10.1109/CAHPC.2002.1180773
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-28
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Cache memory Random access memory Software performance Prefetching Performance gain Performance loss Delay Computer aided instruction Computer architecture
Content Type	Text
Resource Type	Article

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