NDLI: Buffered Crossbar Fabrics Based on Networks on Chip

Content Provider	IEEE Xplore Digital Library
Author	Mhamdi, L. Goossens, K. Senin, I.V.
Copyright Year	2010
Abstract	Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratically with the port count. Additionally, similar to traditional crossbars, point-to-point switching mandates the use of long wires to connect inputs to outputs, resulting in non-negligible delays. In this paper,we propose a CICQ switching architecture where the bufferedcrossbar fabric is designed using a Network on Chip (NoC).Instead of a dedicated buffer for every pair of input-outputports, we use on-chip routers, one for each crosspoint. Our design offers several advantages when compared to traditional CICQs: 1) speedup, because the fabric can operate faster due to the small size of the NoC routers, their distributed arbitration and the short wires connecting them. This is in contrast to single-hopcrossbars that use long wires and centralized arbitration. 2) Load balancing, because flows from different input-output port pairs share the same router buffers, contrary to the internal buffers of traditional CICQs that are dedicated to a single input-output pair. 3) Path diversity, allowing traffic from an input port to follow different paths to its destination output port. This resultsin further load balancing, especially for non-uniform traffic, and provides better fault tolerance in the presence of interconnect failures. We analyzed the performance of our architecture by simulation and presented its performance under wide traffic conditions and switch sizes. We prototyped, in CMOS technology, a 32×32 NoC-based crossbar switch. The implementation results suggest that we can clock the switch at a frequency of 413 MHZ, reaching an aggregate throughput in excess of 10^10 ATM cellsper second.
Starting Page	74
Ending Page	79
File Size	230703
Page Count	6
File Format	PDF
ISBN	9781424462483
e-ISBN	9781424462490
DOI	10.1109/CNSR.2010.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-11
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrics Network-on-a-chip Switches Wires Traffic control Load management CMOS technology Internet Costs Delay Buffered crossbar fabric. Scheduling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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