NDLI: The U1traSPARC T1: A Power-Efficient High-Throughput 32-Thread SPARC Processor

Content Provider	IEEE Xplore Digital Library
Author	Leon, A.S. Sheahan, D.
Copyright Year	2006
Description	Author affiliation: Sun Microsyst. Inc., Sunnyvale (Leon, A.S.; Sheahan, D.)
Abstract	Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power and cooling in today's data centers. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b cores, a high bandwidth interconnect crossbar, a shared 3 MB L2 Cache and four double-width DDR2 DRAM interfaces. Implemented in 90 nm CMOS technology, the 378 $mm^{2}$ die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of applications, including WebServers, data and application servers, Java applications, search, streaming video and Telco applications.
Starting Page	27
Ending Page	30
File Size	6055626
Page Count	4
File Format	PDF
ISBN	0780397347
DOI	10.1109/ASSCC.2006.357843
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-13
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput CMOS technology Process design Cooling Power generation Multithreading Computer architecture Bandwidth Power system interconnection Java throughput performance Chip MultiThreading (CMT) DSA EM GOI high bandwidth NBTI Niagara UltraSPARC T1 reliability low power multicore OpenSPARC power management SSL RSA T1000 T2000 thermal management
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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