NDLI: Synthesis of a timing-error detection architecture

Content Provider	IEEE Xplore Digital Library
Author	Yu-Shih Su Po-Hsien Chang Shih-Chieh Chang TingTing Hwang
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu (Yu-Shih Su; Po-Hsien Chang; Shih-Chieh Chang; TingTing Hwang)
Abstract	Delay variation can cause a design to fail its timing specification. Ernst in D. Ernst, et al., (2003), observes that the worst delay of a design is least probable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their experimental results show significant performance (or power) gain as compared with the worst-case design. However, the architecture in D. Ernst, et al., (2003), suffers the short path problem which is difficult to resolve. In this paper, we propose a novel error-detecting architecture to solve the short path problem. Our experimental results show considerable performance gain can be achieved with reasonable area overhead.
Starting Page	160
Ending Page	163
File Size	335437
Page Count	4
File Format	PDF
ISBN	9781424416165
DOI	10.1109/VDAT.2008.4542437
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-23
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Clocks Latches Timing Computer architecture Design optimization Logic Performance gain Circuits Libraries
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Modeling unbuffered latches for timing analysis

Logic synthesis for better than worst-case designs

Timing optimization of multi-phase sequential logic

Soft-edge flip-flops for improved timing yield: design and optimization

High performance and low power completion detection circuit

Latch Modeling for Statistical Timing Analysis

Design and synthesis for timing error tolerance

On the performance of level-clocked circuits

An Algorithm for Incremental Timing Analysis

Synthesis of a timing-error detection architecture

Similar Documents

Modeling unbuffered latches for timing analysis

Logic synthesis for better than worst-case designs

Timing optimization of multi-phase sequential logic

Soft-edge flip-flops for improved timing yield: design and optimization

High performance and low power completion detection circuit

Latch Modeling for Statistical Timing Analysis

Design and synthesis for timing error tolerance

On the performance of level-clocked circuits

An Algorithm for Incremental Timing Analysis

Synthesis of a timing-error detection architecture