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2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT) - Proceedings of Technical Papers - Title

Table of content

System-level design: a strategic investment for the future of the electronic industry

Challenges and opportunities in nano-scale VLSI design

On statistical correlation based path selection for timing validation

Formal compliance verification of interface protocols

ToggleFinder: accurate RTL power estimation for large designs

Embedded memory diagnostic data compression using differential address

High accuracy jitter measurement using cyclic pulse width modulation structure

Application specific eFPGAs for SoC platforms

Reconfigurable cryptographic RISC microprocessor

Hardware implementations of high-speed network monitors

An efficient and low power systolic squarer

Low-power BIBITS encoding with register relabeling for instruction bus

New architectures for reduced-state sequence detection with local feedback

A DVB-T baseband demodulator design based on multimode silicon IPs

Design and synthesis for timing error tolerance

An efficient power modeling approach for embedded memory using LIB format

Race-condition-aware retiming

Buffered tree refinement considering timing and congestion

Faster min-cut computation in unweighted hypergraphs/circuit netlists

PARSY: a parasitic symmetric router for net bundles using module generators

Reconfigurable architectures for network processing

An area and power efficient frame synchronizer for 480Mb/s OFDM-based UWB system

A 528MS/s frequency synchronizer for OFDM-based UWB system

A dual-band transmitter for IEEE 802.11a/b/g WLAN

Adaptive on-die termination resistors for high-speed transceiver

High speed pilot-less sampling frequency acquisition for OFDM systems

A new channel equalizer for OFDM-based wireless communications

Analog baseband filtering realized using switched capacitor finite impulse response filter

SPEED: synthesis of high-performance large scale analog/mixed signal circuit

A 1.25Gb/s half-rate clock and data recovery circuit

A novel current sensing circuit for a current-mode control CMOS DC-DC buck converter

A low-cost equalizer-based auto-gain-control scheme for high-speed transceiver applications

How to make my chips cool [power supply circuits]

Transient analysis of thermal noise on switch cap circuit

A multiple-row transistor placement system for full custom design

The design of a DSC/DV dual role backend SoC

Challenge and innovation of VLSI design below 100nm

A mixed-signal implementation of a multi-carrier QAM transceiver for optical communications

A 0.35-/spl mu/m SiGe WCDMA direct conversion transmitter with DC offset compensation for carrier leakage reduction

A high linearity low noise amplifier in a 0.35/spl mu/m SiGe BiCMOS for WCDMA applications

A 1.6-GHz delta-sigma modulated fractional-N frequency synthesizer

The limitations in applying analytic design equations for optimal class E RF power amplifiers design

A 0.35/spl mu/m SiGe BiCMOS frequency synthesizer for WCDMA mobile terminals

An accurate design of fully integrated 2.4GHz CMOS cascode LNA

CyberWorkBench: integrated design environment based on C-based behavior synthesis and verification

System-level HW/SW co-simulation framework for multiprocessor and multithread SoC

A hardware/software-concurrent JPEG2000 encoder

An RTOS-based approach to design and validation of embedded systems

System-level performance analysis of embedded system using behavioral C/C++ model

An improved methodology for system-level point-to-point communication architecture synthesis in SOC design

Automatic generation of software/hardware co-emulation interface for transaction-level communication

Efficient test scheduling for hierarchical core based design

Parallel core testing with multiple scan chains by test vector overlapping

Test pattern generation and clock disabling for test time and power reduction

Low-power test pattern generator design for BIST via non-uniform cellular automata

Delay defect coverage for FPGA test configurations based on statistical evaluation

A TLM platform for system-on-chip simulation and verification

Emerging memory technologies - mainstream or hearsay?

0RC2DSP: compiler infrastructure supports for VLIW DSP processors

On-chip bus encoding for LC cross-talk reduction

Delay modeling for buffered RLY/RLC trees

Platform based design of all binary motion estimation (ABME) with bus interleaved architecture

Decomposition of instruction decoder for low power designs

On-chip network evolution using NetC

A 10-Gb/s laser diode driver in 0.35 /spl mu/m BiCMOS technology

Fast switching gigabit/s CMOS burst-mode transmitter for PON applications

10-Gb/s SiGe modulator drivers with 4.5 V/sub pp/ output swing

All digital 625Mbps & 2.5Gbps deskew buffer design

A multilevel sensing and program verifying scheme for Bi-NAND flash memories

Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile

Architecture design of MPEG-4 texture decoder supporting object-based video coding

JPEG2000 encoder architecture design with fast EBCOT algorithm

A low-power H.264/AVC decoder

Design and implementation of an efficient architecture for higher order statistics with DWT

A high-performance low power direct 2-D transform coding IP design for MPEG-4 AVC/H.264 with a switching power suppression technique

Future trends in SoC interconnect

Timing recovery methods for gigabit Ethernet

Design techniques for INL and jitter prediction of a 3.3V 16b 65MSps pipeline ADC core

MIMCAP dynamic leakage impact to switched-capacitor sigma-delta converters in deep-submicron digital CMOS processes

A background comparator calibration technique for flash analog-to-digital converters

A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter

On improving dynamic range of wideband multistage /spl Sigma//spl Delta/ modulator using nonlinear oscillation

Implementation of dynamically reconfigurable processor DAPDNA-2

Instruction set architecture scheme for multiple fixed-width instruction sets and conditional execution

A semi-custom design of branch address calculator in the IBM power4 microprocessor

Lightweight arithmetic units for VLSI digital signal processors

A novel register organization for VLIW digital signal processors

Substrate-bias optimized 0.18/spl mu/m 2.5GHz 32-bit adder with post-manufacture tunable clock

Area and power efficient pattern prediction architecture for filter cache access prediction in the instruction memory hierarchy

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT) (IEEE Cat. No. 05TH8803)

VLSI - Sponsored by / In cooperation with [Back Cover]

Application specific eFPGAs for SoC platforms

Content Provider	IEEE Xplore Digital Library
Author	Noll, T.G.
Copyright Year	2005
Description	Author affiliation: Head of Inst. of Comput. Syst., Aachen Univ. of Technol., Germany (Noll, T.G.)
Abstract	With the continuous progress of CMOS technology the integration of the complete functionality of complex systems becomes feasible on a single die of silicon. Such systems-on-chip (SoC) in future will feature a huge computational power by operating billions of transistors at GHz-clock frequencies. But aside of the well known advantages of systems-on-chip their exploding gate count complexity as well as the physical complexity of future deepsub-micron technologies are facing SoC designers by serious issues. In order to overcome the inevitable problems due to exploding NRE (especially mask) costs the concept of SoC platforms, suited to match the requirements of different customers and applications in a specific domain is applied, allowing to share NRE costs among a high volume of fabricated devices. This platform approach as well as other aspects like the ever-decreasing time-to-market window, need for functionality updates etc. require a high degree of flexibility to be provided on future SoCs. The extensive use of SW-programmable kernels on SoCs offers the highest available flexibility but, although their performance continuously increases, suffers from a too small computational performance for many applications and even more severe is paid for by an unacceptable power penalty. High performance blocks dedicated to standard functionalities (e.g. correlation, filtering, error decoding etc. in frequently used DSP processing) feature orders of magnitude better power and area efficiency but no flexibility at all. An additional implementation alternative attaining more and more attention is the use of reconfigurable embedded FPGA (eFPGA) blocks which allow an attractive compromise between flexibility and efficiency. Especially such eFPGAs seem to be ideally suited as co-processor blocks for efficient acceleration of challenging arithmetic tasks on SW-programmable kernels. The application domain for those reconfigurable accelerators on a SoC platform is quite well defined and therefore they can be tuned to this specific domain, trading flexibility for even better efficiency. As for conventional FPGA devices it is well known, that the communication and reconfiguration overhead contributes with up to 90% to the total power dissipation and silicon area main attention has to be spent on the optimization of communication and reconfiguration resources. Optimization strategies as well as the feasible optimization potential of application specific eFPGAs are presented.
Sponsorship	Ind. Technol. Res. Inst., Taiwan
File Size	144251
File Format	PDF
ISBN	0780390601
DOI	10.1109/VDAT.2005.1500011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-27
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Silicon Costs Kernel Field programmable gate arrays Frequency Time to market High performance computing Filtering Decoding
Content Type	Text
Resource Type	Article

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