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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Liu Youyao Han Jungang |
| Copyright Year | 2012 |
| Description | Author affiliation: Sch. of Electron. Eng., Xi'an Univ. of Posts & Telecommun., Xi'an, China (Liu Youyao; Han Jungang) |
| Abstract | With the feature size of semiconductor technology reduced and (Intellectual Properties) IP cores increased, on chip interconnection network architectures have a great influence on the performance and area of System-on-Chip(SoC) design. Focusing on trade-off performance, cost and implementation, a regular Network-on-Chip NoC architecture, named Mesh-Connected Rings (MCR) interconnection network, is proposed. The topology of MCR is simple, planar and scalable in architecture, which combines Mesh with Ring. A detailed theoretical analysis for MCR and Mesh is given, and a simulation analysis based on the virtual channel router with wormhole switching is also presented. The results compared with the general Mesh architecture show that MCR has better performance, especially in local traffics and low loads, and lower cost. |
| Starting Page | 719 |
| Ending Page | 724 |
| File Size | 291927 |
| Page Count | 6 |
| File Format | |
| ISBN | 9780769548791 |
| e-ISBN | 9780769548791 |
| DOI | 10.1109/PDCAT.2012.142 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-12-14 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Network topology Topology Routing Multiprocessor interconnection Throughput Structural rings Clocks System-on-Chip; Network-on-Chip; Network Topology; Routing Algorithms; Performance evaluation |
| Content Type | Text |
| Resource Type | Article |
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