NDLI: Toward Millimeter-Wave DACs: Challenges and Opportunities

Content Provider	IEEE Xplore Digital Library
Author	Khalil, W. Wilson, J. Dupaix, B. Balasubramanian, S. Creech, G.L.
Copyright Year	2012
Abstract	As line widths in emerging III-V technologies approaching that of modern CMOS, the conception of high performance mixed signal designs such as digital to analog converters (DACs) in the mm-wave space becomes possible. While addressing the speed limitations, candidate III-Vs ((InP, GaAs and GaN) are known to suffer from increased switching power consumption, limited device yield and absolute accuracy. CMOS, on the other hand, has the benefit of low-power digital switching, fine resolution and scalability. Recent attempts in marrying the two technologies have been carried out in the DARPA COSMOS program, by integrating III-V type devices with CMOS circuits, so as to exploit the advantages of low-power digital CMOS and high-speed high-power InP. This paper presents some of the challenges as well as prospects in designing record speed and performance DACs in the COSMOS program while contrasting it to that of deeply-scaled CMOS. A multi-phase parallel DAC architecture is leveraged for ultra-wideband synthesis, to improve noise performance and achieve higher information rates. The architectural bounds between CMOS and InP as well as detailed circuit-level analysis of critical block elements will be highlighted.
Starting Page	1
Ending Page	4
File Size	597385
Page Count	4
File Format	PDF
ISBN	9781467309288
ISSN	15508781
e-ISBN	9781467309295
DOI	10.1109/CSICS.2012.6340078
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Indium phosphide CMOS integrated circuits Clocks Switching circuits Impedance Delay
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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