NDLI: FPGA implementation of blind adaptive decision feedback equalizer

Content Provider	IEEE Xplore Digital Library
Author	Ashmawy, D. Abdel-Raheem, E. Mansour, H. Youssif, M. Mohanna, M.
Copyright Year	2009
Description	Author affiliation: ECE Dept., University of Windsor, Ontario, Canada (Abdel-Raheem, E.) \|\| Seismology Dept., NRIAG, Cairo, Egypt (Mohanna, M.) \|\| ECE Dept., Benha University, Cairo, Egypt (Ashmawy, D.; Mansour, H.) \|\| ECE Dept., Al-Azhar University, Cairo, Egypt (Youssif, M.)
Abstract	This paper considers field programmable gate array (FPGA) implementations for blind adaptive decision feedback equalizer (DFE) based on the IP core reported in [1]. The design can achieve channel equalization for 16-QAM and 64-QAM. Constant modulus algorithm (CMA) and multi-modulus algorithm (MMA) are considered for update the coefficients in the blind mode of operation which are followed by decision-directed (DD) mode. The system can work at a maximum clock frequency of 22 MHz. The design steps first consider fixed-point simulations using MATLAB fixed-point toolbox follows by FPGA implementations. The implementations are divided into complex weight update module, output computation module, error adjustment module, and decision device module. Finally, the DFE is implemented using Xilinx Virtex-II XC2VP100 FPGA.
Starting Page	495
Ending Page	500
File Size	8479440
Page Count	6
File Format	PDF
ISBN	9781424459490
e-ISBN	9781424459506
DOI	10.1109/ISSPIT.2009.5407537
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	United Arab Emirates
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Decision feedback equalizers Finite impulse response filter AWGN Distortion Quadrature amplitude modulation Signal design Pulse modulation Seismology Adaptive arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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