NDLI: Implementation of High Data Rate Stream Parsing with Data Aligning Mechanism

Content Provider	IEEE Xplore Digital Library
Author	Mladenov, T.M. Mujahid, F.A. Jung, E. Har, D.
Copyright Year	2006
Description	Author affiliation: Dept. of Inf. & Commun., Gwangju Inst. of Sci. & Technol. (Mladenov, T.M.; Mujahid, F.A.; Jung, E.; Har, D.)
Abstract	Nowadays the HDTV (high definition television) is growing more and more popular. In many cases a compression of this high quality multimedia data is needed for storing or transmitting purposes. In order to preserve good quality, the compressed stream should have high data rate. It is also common case to combine several such streams, representing different programs, into one single multimedia stream. Here comes the need of high data rate multiplexing and demultiplexing. To operate with high data rate stream, the clock frequency, the word width or both have to be increased. For cost efficient FPGA implementation the wider word width is preferred, which allows smaller in logic and slower in speed FPGA to be used. In this paper the issues following this choice are revealed and a data aligning implementation technique is proposed
Starting Page	697
Ending Page	701
File Size	300092
Page Count	5
File Format	PDF
ISBN	0780397533
DOI	10.1109/ISSPIT.2006.270889
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-27
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Streaming media Transform coding HDTV Decoding TV Demultiplexing Field programmable gate arrays Video compression Testing Signal resolution MPEG-2 data aligning FPGA demultiplexing
Content Type	Text
Resource Type	Article

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