NDLI: Pipelined concurrent simulation on distributed-memory parallel computers

Content Provider	IEEE Xplore Digital Library
Author	Tai, S.-E. Bhattacharya, D.
Copyright Year	1991
Description	Author affiliation: Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA (Tai, S.-E.; Bhattacharya, D.)
Abstract	Presents a space- and time-efficient approach to fault simulation on distributed-memory message-passing parallel computers. The processors in the parallel machine, and the host, communicate in a pipelined fashion where each processor simulates only one partition of the circuit under consideration using the concurrent simulation approach. If good load balancing can be obtained, this approach leads to nearly linear speedup when a large number of vectors are simulated. Further, practical implementations of this approach uses memory in the parallel machine efficiently. A preliminary implementation of this approach on an Intel hypercube machine is then described. Experimental results obtained using the ISCAS85 benchmark circuits confirm the prediction that the actual speedup is primarily dependent on the load distribution across processors. Further, simple circuit partitioning heuristic is seen to provide moderate to good speedup in most cases.
Starting Page	63
Ending Page	68
File Size	457931
Page Count	6
File Format	PDF
ISBN	0818621257
DOI	10.1109/ISVD.1991.185094
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-01-04
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Computational modeling Parallel machines Circuit faults Computer simulation Concurrent computing Distributed computing Load management Vectors Hypercubes
Content Type	Text
Resource Type	Article

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