NDLI: Workload characterization for the design of future servers

Content Provider	IEEE Xplore Digital Library
Author	Maron, B. Chen, T. Vianney, D. Olszewski, B. Kunkel, S. Mericas, A.
Copyright Year	2005
Description	Author affiliation: IBM Corp., Austin, TX, USA (Maron, B.; Chen, T.; Vianney, D.; Olszewski, B.; Kunkel, S.; Mericas, A.)
Abstract	Workload characterization has become an integral part of the design of future servers since their characteristics can guide the developers to understand the workload requirements and how the underlying architecture would optimize the performance of the intended workload. In this paper, we give an overview of the POWER5 architecture. We also introduce the POWER5 performance monitor facilities and performance events that lead to the construction of a CPI (cycles per instruction) breakdown model. For our study, we characterize four different groups of workloads: commercial, HPC, memory, and scientific. Using the data obtained from the POWER5 performance counters, we breakdown the CPI stack into a base component, when the processor is completing work and a stall component when the processor is not completing instructions. The stall component can be further divided into cycles when the pipeline was empty and cycles when the pipeline was not empty but completion is stalled. With this model, we enumerate the number of processing cycles, i.e., a fraction of the CPI, a workload spent while progressing through the core resources and the incurred penalty upon encountering those resource usage inhibitors. The results show the CPI breakdown for each workload, identify where each workload spends its processing cycles and the associated CPI cost when accessing the core resources.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on Comput. Archit
Starting Page	129
Ending Page	136
File Size	433357
Page Count	8
File Format	PDF
ISBN	0780394615
DOI	10.1109/IISWC.2005.1526009
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Control systems Electric breakdown Hardware Registers Size control Delay Memory management Decoding Design optimization
Content Type	Text
Resource Type	Article

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