NDLI: A High Performance Scalable FFT

Content Provider	IEEE Xplore Digital Library
Author	Nash, J.G.
Copyright Year	2007
Description	Author affiliation: Centar, Los Angeles, CA (Nash, J.G.)
Abstract	An FPGA implementation of a fast Fourier transform (FFT) circuit is described as an example of a new class of parallel FFT architectures that can provide better performance and functionality than traditional pipelined FFTs and is well suited to wireless applications. Any circuit implementation can perform any transform size that is a multiple of 256 as long as adequate memory is provided. Throughput can be adjusted by adding/subtracting identical blocks of hardware. Power is minimized by using only small memories, providing systolic data flow to avoid memory reads/writes, and localizing connections to reduce interconnect overhead. High dynamic range is obtained through a unique multiple block floating point (BFP) feature. The design is regular in structure and is built with only three simple cells. An FPGA based demonstration circuit with 89db signal-to-quantization-noise has been implemented that can perform a 256-point transform continuously at 0.66 musec/transform. Circuit comparisons are made with a modern commercial pipelined FFT.
Starting Page	2367
Ending Page	2372
File Size	295984
Page Count	6
File Format	PDF
ISBN	1424406587
ISSN	15253511
DOI	10.1109/WCNC.2007.442
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-11
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	OFDM Field programmable gate arrays Flexible printed circuits Hardware Read-write memory Discrete transforms Fourier transforms Discrete Fourier transforms Wireless application protocol System performance
Content Type	Text
Resource Type	Article

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