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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chapman, G.H. Canter, J.M. Cohen, S.S. |
| Copyright Year | 1989 |
| Description | Author affiliation: MIT Lincoln Lab., Lexington, MA, USA (Chapman, G.H.; Canter, J.M.; Cohen, S.S.) |
| Abstract | Restructurable VLSI wafer-scale circuits have been built using two methods, both using laser energy to create low resistance connections between bus lines on already existing circuits. In one technique verticle connections of about 10 Omega are made up from top metal, through silicon nitride, to first metal lines. The other involves melting of silicon in the gap between two implant regions, with the lateral diffusion of dopants creating connections of about 100 Omega . Details of the linking structures, their characteristics, and the apparatus used to interconnect them are described. |
| Starting Page | 21 |
| Ending Page | 29 |
| File Size | 562099 |
| Page Count | 9 |
| File Format | |
| ISBN | 0818699019 |
| DOI | 10.1109/WAFER.1989.47532 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-06-03 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wafer scale integration Laser beam cutting Integrated circuit interconnections Circuit testing Dielectrics and electrical insulation Laboratories Very large scale integration Silicon Joining processes Metal-insulator structures |
| Content Type | Text |
| Resource Type | Article |
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