NDLI: New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits

Content Provider	IEEE Xplore Digital Library
Author	Hiibner, M. Schuck, C. Kiihnle, M. Becker, J.
Copyright Year	2006
Description	Author affiliation: Inst. fur Technik der Informationsverarbeitung, Karlsruhe Univ. (Hiibner, M.; Schuck, C.; Kiihnle, M.; Becker, J.)
Abstract	Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures has to be considered. Here, exploitation of real-time and on-demand reconfiguration of silicon area personalized on suitable granularities demonstrates high situation adaptivity and perspectives for next generation microelectronics. This paper discusses our implemented, synthesized and tested on-demand and partial reconfiguration approaches for fine-grain (Xilinx Virtex FPGAs) data paths. This includes also very new dynamic and partial reconfiguration for 2D placement and routing adaptation for today's fine-grain Xilinx FPGAs
File Size	563716
File Format	PDF
ISBN	0769525334
DOI	10.1109/ISVLSI.2006.67
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-02
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microelectronics Circuits Field programmable gate arrays Time to market Costs Energy consumption Embedded system System-on-a-chip Runtime Silicon
Content Type	Text
Resource Type	Article

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