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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xin Hua Hantao Zhang |
| Copyright Year | 1992 |
| Description | Author affiliation: Dept. of Comput. Sci., Iowa Univ., Iowa City, IA, USA (Xin Hua; Hantao Zhang) |
| Abstract | Formal hardware design verification is to examine whether a structural specification of a circuit meets its behavioral specification. Despite the progress in formal verification, there is a big gap between hardware designers and verifiers, partially because there are no common specification languages for them to use. The authors show that formal semantics could bridge such a gap. By providing an axiomatic semantics to an existing hardware design language called the Iowa logic specification language (ILSL), the authors show that a circuit description in ILSL can be automatically converted into a set of first-order formulas which is the semantic description of the circuit and is acceptable by an existing theorem prover called the rewrite rule laboratory (RRL). In particular, they show how iterative statements of ILSL are converted into recursive functions of RLL. Their work thus results in a uniform specification language in which both hardware design and automatic verification can be done. |
| Starting Page | 183 |
| Ending Page | 190 |
| File Size | 510781 |
| Page Count | 8 |
| File Format | |
| ISBN | 0818626100 |
| DOI | 10.1109/GLSV.1992.218347 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1992-02-28 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Specification languages Bridge circuits Formal verification Signal design Computer science Cities and towns Logic design Logic circuits Laboratories |
| Content Type | Text |
| Resource Type | Article |
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