NDLI: Use of statecharts-related description to achieve testable design of control subsystems

Content Provider	IEEE Xplore Digital Library
Author	Fummi, F. Sami, M.G. Tartarini, F.
Copyright Year	1997
Description	Author affiliation: Dipt. di Elettronica, Politecnico di Milano, Italy (Fummi, F.)
Abstract	Control-dominated architectures are efficiently described by means of graphical representations based on statecharts. Statecharts descriptions can be automatically translated into HDL representations (VHDL or Verilog) which are directly synthesized into gate-level netlists. This paper describes a set of rules which transform, if possible, a statecharts description into a simpler representation based on hierarchically interconnected FSMs (HFSM). The comparison of the HFSM description with the gate-level synthesized net-list allows to efficiently perform redundancies removal and test pattern generation. Thus, by applying the proposed testing strategy, fully testable implementations can be obtained even for such devices which cannot be satisfactorily analyzed at the gate level only.
Starting Page	118
Ending Page	123
File Size	645219
Page Count	6
File Format	PDF
ISBN	0818679042
ISSN	10661395
DOI	10.1109/GLSV.1997.580513
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-03-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Hardware design languages Automatic control Test pattern generators Control systems Circuit testing Redundancy Automatic testing Pattern analysis Sequential circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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