NDLI: Improving self-timed pipeline ring performance through the addition of buffer loops

Content Provider	IEEE Xplore Digital Library
Author	Hai Zhao Sabine, N.M. Edwin Hsing-Mean Sha
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA (Hai Zhao; Sabine, N.M.; Edwin Hsing-Mean Sha)
Abstract	While self-timed pipelines have overcome the problem of clock skew which degrades the performance of synchronous pipelines, the improvement is not without its cost; self-timed pipelines are forced to spend a larger amount of time on communication than their synchronous counterparts. This has led researchers to search for ways to improve the performance of self-timed pipelines by changing the communication scheme in an effort to reduce the communication delay. Our approach divides the total communication time into two parts: data communication delay and pace handshaking overhead. By adding buffer loops to each stage of a self-timed pipeline, we can reduce the pace handshaking overhead; thus decreasing the total time spent on communication. One important result of this design innovation has been the simplification of analysis needed to find the best initial system configuration. With our design, the same initial system configuration may be chosen regardless of computation time and variations in computation time. In addition, our design has a lower average cycle time than the traditional self-timed pipeline, which leads to an increase in performance.
Starting Page	218
Ending Page	223
File Size	506970
Page Count	6
File Format	PDF
ISBN	0818670355
ISSN	10661395
DOI	10.1109/GLSV.1995.516056
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-03-16
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Clocks Performance analysis Computer science Degradation Costs Data communication Delay effects Technological innovation Computational modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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