NDLI: Testable design for BiCMOS stuck-open fault detection

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Testable design for BiCMOS stuck-open fault detection

Content Provider	IEEE Xplore Digital Library
Author	Menon, S.M. Jayasumana, A.P. Malaiya, Y.K.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng., Colorado State Univ., Ft. Collins, CO, USA (Menon, S.M.; Jayasumana, A.P.)
Abstract	BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.
Starting Page	296
Ending Page	302
File Size	659085
Page Count	7
File Format	PDF
ISBN	0818638303
DOI	10.1109/VTEST.1993.313362
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-04-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	BiCMOS integrated circuits Fault detection Circuit faults Delay Circuit testing Electrical fault detection Logic testing Design for testability Logic gates Logic design
Content Type	Text
Resource Type	Article

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