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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bo Yao Sinha, A. Pomeranz, I. |
| Copyright Year | 2013 |
| Description | Author affiliation: Intel Corp., Hillsboro, OR, USA (Sinha, A.) || Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Bo Yao; Pomeranz, I.) |
| Abstract | We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 301088 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467355421 |
| ISSN | 10930167 |
| e-ISBN | 9781467355438 |
| DOI | 10.1109/VTS.2013.6548902 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-04-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delays Circuit faults Fault diagnosis Integrated circuit modeling Inverters Correlation static timing Delay testing input necessary assignments path selection |
| Content Type | Text |
| Resource Type | Article |
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