NDLI: Automated Debug of Speed Path Failures Using Functional Tests

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Table of Contents

Program Committee

Steering Committee

Acknowledgements

Test Technology Technical Council (TTTC)

Test Technology Educational Program (TTEP) Tutorials

Efficient Array Characterization in the UltraSPARC T2

Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller

Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects

Small Delay Fault Model for Intra-Gate Resistive Open Defects

Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip-Flop Testing

Soft-Error Hardening Designs of Nanoscale CMOS Latches

Exploiting Unused Spare Columns to Improve Memory ECC

An Adaptive-Rate Error Correction Scheme for NAND Flash Memory

Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric

Recursive Path Selection for Delay Fault Testing

A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification

Automated Selection of Signals to Observe for Efficient Silicon Debug

A New Post-Silicon Debug Approach Based on Suspect Window

Automated Debug of Speed Path Failures Using Functional Tests

Output Hazard-Free Transition Delay Fault Test Generation

Efficient Scheduling of Path Delay Tests for Latch-Based Circuits

Effective and Efficient Test Pattern Generation for Small Delay Defect

Panel: Apprentice - VTS Edition: Season 2

DFT and Test Problems from the Trenches

Multiple-Fault Diagnosis Using Faulty-Region Identification

Predictive Test Technique for Diagnosis of RF CMOS Receivers

Controlling DPPM through Volume Diagnosis

Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions

The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost

A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections

False Path Aware Timing Yield Estimation under Variability

Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study

Yield and Cost Analysis of a Reliable NoC

Restrict Encoding for Mixed-Mode BIST

A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset

Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors

Physically-Aware N-Detect Test Relaxation

Automatic Selection of Internal Observation Signals for Design Verification

STDF Memory Fail Datalog Standard

Testing for Transistor Aging

Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths

Understanding Power Supply Droop during At-Speed Scan Testing

Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest

Special Session 8: New Topics: At-Speed Testing in the Face of Process Variations

Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips

Highly X-Tolerant Selective Compaction of Test Responses

Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure

Maintaining Accuracy of Test Compaction through Adaptive Re-learning

RT-Level Deviation-Based Grading of Functional Test Sequences

Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering

DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study

On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector

Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC

A Time Domain Method to Measure Oscillator Phase Noise

A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources

Design-for-Testability for Digital Microfluidic Biochips

Stuck-Open Fault Leakage and Testing in Nanometer Technologies

SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration

Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA

Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and Testing

Panel: Analog Characterization and Test: The Long Road to Realization

Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough?

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Automated Debug of Speed Path Failures Using Functional Tests

Content Provider	IEEE Xplore Digital Library
Author	McLaughlin, R. Venkataraman, S. Lim, C.
Copyright Year	2009
Abstract	Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. In this paper, we present a technique to automate the debug of speed path failures using failing functional tests by extracting information from design-for-debug features and then algorithmically isolating the internal speed-paths that could be the source of the failures. Results from application of the technique during silicon debug on the Intel ® Core ™ i7 quad-core processor is presented.
Starting Page	91
Ending Page	96
File Size	790111
Page Count	6
File Format	PDF
ISBN	9780769535982
ISSN	10930167
DOI	10.1109/VTS.2009.53
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Silicon Timing System testing Frequency Computer bugs Circuit simulation Microprocessors Data mining Algorithm design and analysis functional tests Silicon debug speed-path timing design for debug
Content Type	Text
Resource Type	Article

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