NDLI: DSP-based statistical self test of on-chip converters

Content Provider	IEEE Xplore Digital Library
Author	Hak-soo Yu Sungbae Hwang Abraham, J.A.
Copyright Year	2003
Description	Author affiliation: Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA (Hak-soo Yu; Sungbae Hwang; Abraham, J.A.)
Abstract	We propose a DSP-based statistical self test approach for testing on-chip data converters. Analog to digital converters (ADCs) and digital to analog converters (DACs) can be tested in a loop-back mode, providing a go/no-go result; however such tests focus on catastrophic fault coverage. We develop a technique for testing converters in loop-back mode which is simple, but has good parametric as well as catastrophic fault coverage. We use the on-chip digital signal processing unit to generate test stimuli. The analysis of the results is done through the use of software on the DSP unit which is capable of monitoring primary inputs, outputs and/or internal nodes. Characterization of actual /spl Delta//spl Sigma/ converters was performed to show the feasibility of the proposed method.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	83
Ending Page	88
File Size	361851
Page Count	6
File Format	PDF
ISBN	0769519245
ISSN	10930167
DOI	10.1109/VTEST.2003.1197637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Circuit testing Circuit faults Noise shaping Monitoring Frequency Analog-digital conversion Digital signal processing Built-in self-test Digital-analog conversion
Content Type	Text
Resource Type	Article

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