NDLI: Analysis of hot-carrier degradation in 0.25-/spl mu/m surface-channel pMOSFET devices

Content Provider	IEEE Xplore Digital Library
Author	Liu, C.H. Chen, M.G. Shiang Huang-Lu Chang, Y.J. Fu, K.Y.
Copyright Year	1999
Description	Author affiliation: United Microelectron. Corp., Hsin-Chu City, Taiwan (Liu, C.H.)
Abstract	Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs/spl ap/Vth, Vgs/spl ap/Vds//sup 2/, and Vgs/spl ap/Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs/spl ap/Vth results in the worst-case damage, in which a "turn-around" behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-/spl mu/m or longer p-channel devices to the best of our knowledge). This turnaround behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-/spl mu/m pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.
Starting Page	82
Ending Page	85
File Size	228110
Page Count	4
File Format	PDF
ISBN	0780356209
DOI	10.1109/VTSA.1999.786005
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-06-10
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hot carriers Degradation MOSFET circuits Stress Electron traps Interface states Cause effect analysis Hot carrier effects
Content Type	Text
Resource Type	Article

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Edge effect under temperature bias stress of 0.18 /spl mu/m PMOS technology

Dynamic effects in hot-carrier degradation relevant for CMOS operation

Hot-carrier-induced degradation on 0.1/spl mu/m partially depleted SOI CMOSFET

Positive oxide-charge generation during 0.25 /spl mu/m PMOSFET hot-carrier degradation

Lateral field enhanced band-trap-band tunneling current in a 0.5 /spl mu/m "off" state mosfet

New hot-carrier degradation mechanisms in 0.25 /spl mu/m PMOSFETs

Hot-carrier induced instability of 0.5 mu m CMOS devices patterned using synchrotron X-ray lithography

Effects of interface traps and bulk traps in SiO/sub 2/ on hot-carrier-induced degradation

Reliability effects in 0.15 /spl mu/m low dose SIMOX N-MOSFETs designed for low power/low voltage applications

Analysis of hot-carrier degradation in 0.25-/spl mu/m surface-channel pMOSFET devices

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