NDLI: Gate Current Injection in Submicron EPROM Cells

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Foreword: Welcome to the Fourth Symposium on VLSI Technology in San Diego

1984 VLSI Symposium Committee

VLSI Design for Testability

A Buried Giga-Ohm Resistor(BGR) Load Static RAM Cell

A 2 μm Stacked CMOS 64K SRAM

A High Performance 128k (32K × 4) NMOS RAM

A High Latch-Up Immunity Full CMOS RAM

An Aluminum Gate One Megabit DRAM

A Vertical Capacitor Cell for ULSI DRAM's

High Capacitance Trench Structure (HI-CAT) for Megabit LSI

Multilevel Metallization Technology for VLSIs

Wiring Capacitance Simulation in Two and Three Dimensions

A Fully Scaled Half-Micrometer NMOS Technology Using Direct-Write E-Beam Lithography

A New Trench Isolation Technique for MOS VLSI

Work Function Controlled Silicide Technology for Submicron CMOS

Characterization of LPCVD Aluminun for VLSI Processing

High Performance Silicided Source/Drain CMOSFET Without Parasitic Effects

Multilevel Interconnection for VLSI

A High Speed 1mb Eprom with Ti Silicided Gate

Poly-Oxide/Nitride/Oxide Structures for Highly Reliable EPROM Cells

EEPROM Cell with HB (One Half Barrier Height) Oxide for VLSI

3-Dimensional Gate Array with Vertically Stacked Dual SOI/CMOS Structure Fabricated by Beam Recrystallization

Bi-CMOS Circuits for High Performance VLSI

Multiport Register File Architecture

A 1.1 NS Access Time 4 Kb Bipolar RAM Using Super Self-Aligned Technology

An ECL 4K-Bit Bipolar RAM with an Effective Access Time of 2.5NS and On-Chip Address Latches

Characterization of Bipolar Transistors with Polysilicon Emitter Contacts

Disilane Photo-Epitaxy for VLSI

A 120-Mw, 8-bit, Video-Frequency A/D Converter with Shallow-Groove-Isolated Bipolar VLSI Technology

Image Enhancement in High-Resoltuion Lithography Through Polymer Grafting Techniques

An Electronic Digital Vernier for Process Evaluation

Holographic Submicron Photolithography

High Precision VLSI Patterning Technology for E-Beam Direct Writing Process

A Review of Recent Developments in Focused Ion Beam Applications

A Sub-Micron Electron-Beam Direct Writing for 1 μm Thick Negative Resist

Electrical End Point Detection of Plasma Etched IC Contact Openings

A New Anisotropic Etching of N+ Poly-Si Using XeCl Excimer Laser Beam

Characterization of Submicrometer Buried-Channel and Surface-Channel PMOSFETS

Small Geometry MOS Transistor Measurements and Observed Short and Narrow Channel Effects

Characterization of Intrinsic Capacitances of Small-Geometry MOSFET's

Gate Current Injection in Submicron EPROM Cells

Hot Carrier Injection in Submicron MOSFETs Fabricated by Rapid Isothermal Annealing

Hot-Electron Substrate Current Generation During Switching Transients

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Integrated MOS Devices in Double Active Layers

1983 Symposium on VLSI Technology. Digest of Technical Papers

1982 Symposium on VLSI Technology. Digest of Technical Papers

1981 Symposium on VLSI Technology. Digest of Technical Papers

Gate Current Injection in Submicron EPROM Cells

Content Provider	IEEE Xplore Digital Library
Author	Sato, Masaki Yoshikawa, Kuniyoshi Mori, Seiichi Kanzaki, Kohichi
Copyright Year	1984
Description	Author affiliation: Semiconductor Device Engineering Laboratory Toshiba Corporation 1-Komukai toshiba-cho, Saiwai-ku, Kawasaki, 210, Japan (Sato, Masaki; Yoshikawa, Kuniyoshi; Mori, Seiichi; Kanzaki, Kohichi)
Abstract	Hot electron generation is enhanced by controlling impurity profiles in deeper region from the surface. Reduction of gate oxide thickness, also increases the gate current even under the constant substrate current. It should be noted that the increase of deep channel concentration causes worse influence to long term instability in submicron MOSFET's, therefore separately optimized peripheral devices were combined with EPROM cell. As a result, EPROM cell with 0.9 ¿m gate length, 180Å 1st gate oxide thickness and 2x1017 cm-3 deep boron concentration is designed and 100 ¿sec programming speed under 5V of drain voltage is successfully demonstrated.
Starting Page	82
Ending Page	83
File Size	310816
Page Count	2
File Format	PDF
ISBN	4930813085
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1984-09-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Japan Society of Applied Physics
Subject Keyword	EPROM Boron Threshold voltage Impurities Electrons CMOS process Hot carriers Current measurement Length measurement Magnetooptic recording
Content Type	Text
Resource Type	Article

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