NDLI: A novel pillar DRAM cell for 4 Gbit and beyond

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Table of contents

Chemical mechanical polishing: the impact of a new technology on an industry

Lithography solutions for sub-0.1 /spl mu/m generations

A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization

1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells

A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM

A high-performance sub-0.25 /spl mu/m CMOS technology with multiple thresholds and copper interconnects

An inlaid CVD Cu based integration for sub 0.25 /spl mu/m technology

An evaluation of Cu wiring in a production 64 Mb DRAM

Copper drift in low-K polymer dielectrics for ULSI metallization

A Cu/low-/spl kappa/ dual damascene interconnect for high performance and low cost integrated circuits

The impact of isolation pitch scaling on V/sub TH/ fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetration

Improved 0.12 /spl mu/m EB direct writing for Gbit DRAM fabrication

A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM

A novel pillar DRAM cell for 4 Gbit and beyond

Interconnect scaling: signal integrity and performance in future high-speed CMOS designs

Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chip

A novel air gap integration scheme for multi-level interconnects using self-aligned via plugs

Low resistance dual damascene process by new Al reflow using Nb liner

Novel poly-Si/Al/sub 2/O/sub 3//poly-Si capacitor for high density DRAMs

Dynamic stressing effects on reliability of strontium titanate (SrTiO/sub 3/) thin film capacitors for high-density memory applications

Properties of SrBi/sub 2/Ta/sub 2/O/sub 9/ thin films grown by MOCVD for high density FeRAM applications

Dielectric breakdown, reliability and defect density of (Ba/sub 0.7/Sr/sub 0.3/)TiO/sub 3/ (BST)

A perfect process compatible 2.49 /spl mu/m/sup 2/ embedded SRAM cell technology for 0.13 /spl mu/m-generation CMOS logic LSIs

Highly scalable and fully logic compatible SRAM cell technology with metal damascene process and W local interconnect

A novel high density, low voltage SRAM cell with a vertical NDR device

A novel 6.4 /spl mu/m/sup 2/ full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25 /spl mu/m-generation CMOS technology

Channel size dependence of dopant-induced threshold voltage fluctuation [deep submicron MOSFETs]

Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology

Ultra low power supply voltage (0.3 V) operation with extreme high speed using bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced fast-signal-transmission shallow well

Channel engineering of 0.13 /spl mu/m nMOSFET for 1.0 V CMOS using gate poly-Si oxidation and laterally profiled, surface concentrated channel technologies

An evaluation of X-ray lithography using a 0.175 /spl mu/m (0.245 /spl mu/m/sup 2/ cell area) 1 Gb DRAM technology

A 0.15 /spl mu/m KrF lithography for 1 Gb DRAM product using highly printable patterns and thin resist process

ARC for sub-0.18 /spl mu/m logic and gigabit DRAM frontend and backend processes

Channel engineering using B/sub 10/H/sub 14/ ion implantation for low Vth and high SCE immunity of buried-channel PMOSFETs in 4-Gbit DRAMs and beyond

A 50-GHz 0.25-/spl mu/m high-energy implanted BiCMOS (HEIBiC) technology for Low-Power high-integration wireless-communication systems

CMOS RF modeling for GHz communication IC's

RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip

A study of self-align doped channel structure for low power and low l/f noise operation

A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories

A low voltage operating flash memory cell with high coupling ratio using horned floating gate with fine HSG

A novel step stack NOR cell for low voltage flash

A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND flash memories

Comprehensive study on AC characteristics in SOI MOSFETs for analog applications

A dynamic depletion SOI MOSFET model for SPICE

A 0.18 /spl mu/m fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation

Benefits of SiF/sub 3//sup +/ implanted titanium silicides in advanced CMOS fabrication

A highly reliable 1T/1C ferroelectric memory

High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics

A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs

Normally-off PLED (Planar Localised Electron Device) for non-volatile memory

Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs

33 nm ultra-shallow junction technology by oxygen-free and point-defect reduction process

High performance RF characteristics of raised gate/source/drain CMOS with Co salicide

Direct channel length determination of sub-100 nm MOS devices using scanning capacitance microscopy

Direct Channel Length Determination Of Sub-100nm Mos Devices Using Scanning Capacitance Microscopy

Excellent process control technology for highly manufacturable and high performance 0.18 /spl mu/m CMOS LSIs

Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay

A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology

A manufacturable and modular 0.25 /spl mu/m CMOS platform technology

Electromigration of submicron Damascene copper interconnects

A new prediction method for oxide lifetime and its application to study dielectric breakdown mechanism

Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides

A new degradation scheme for direct-tunneling ultrathin gate dielectric

CVD photoresist processes for sub-0.18 design rules

A novel resist and post-etch residue removal process using ozonated chemistries

A statistical gate CD control including OPC

A novel etch chemistry for low-damage poly-Si gate patterning

A new mode of hot carrier degradation in 0.18 /spl mu/m CMOS technologies

Temperature dependence of substrate current and hot carrier-induced degradation at low drain bias

Deuterium process of CMOS devices: new phenomena and dramatic improvement

Limitation of post-metallization annealing due to hydrogen blocking effect of multilevel interconnect

Highly-reliable, low-resistivity bcc-Ta gate MOS technology using low-damage Xe-plasma sputtering and Si-encapsulated silicidation process

Highly uniform heteroepitaxy of cobalt silicide by using Co-Ti alloy for sub-quarter micron devices

Optimized poly-Si/sub 1-x/Ge/sub x/-gate technology for dual gate CMOS application

Pure Ge mid-gap gate within an industrial high performance and low standby current 0.18 /spl mu/m CMOS process

Microscopic and statistical approach to SILC characteristics-exponential relation between distributed Fowler Nordheim coefficients and its physical interpretation

Gate-oxide degradation from source/drain (S/D) boron diffusion

Local mechanical stress induced defects for Ti and Co/Ti silicidation in sub-0.25 /spl mu/m MOS-technologies

Impact on soft error rate of using platinum electrodes in 1 Gb DRAMs

Trench transformation technology using hydrogen annealing for realizing highly reliable device structure with thin dielectric films

A new STI process based on selective oxide deposition [for CMOS logic]

A shallow trench isolation with SiN guard-ring for sub-quarter micron CMOS technologies

Characterization and elimination of trench dislocations

Stacked gate dielectrics with TaO for future CMOS technologies

Highly robust ultra-thin gate dielectric for giga scale technology

Nitrogen concentration optimization for down-scaled CMOSFET with N/sub 2/O-based oxynitride process

Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology

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A novel pillar DRAM cell for 4 Gbit and beyond

Content Provider	IEEE Xplore Digital Library
Author	Hyun-Jin Cho Nemati, F. Griffin, P.B. Plummer, J.D.
Copyright Year	1998
Description	Author affiliation: Center for Integrated Syst., Stanford Univ., CA, USA (Hyun-Jin Cho)
Abstract	A novel structure and fabrication process for a DRAM cell for 4 Gbit and beyond is proposed. A poly-Si pillar transistor is formed on top of a trench capacitor with the top of the pillar transistor being directly connected to the bit line. In order to reduce the process steps, word line formation by a spacer etch and self-aligned bit line contact using CMP process are developed. XTEM micrographs show almost single grain and less defect in the small pillars after crystallization annealing of prepatterned /spl alpha/-Si. Electrical measurements show that the pass transistor has good subthreshold slope and Id-Vd characteristics. Improvements in the device performance has been achieved by a sacrificial oxidation and hydrogenation.
Starting Page	38
Ending Page	39
File Size	383601
Page Count	2
File Format	PDF
ISBN	0780347706
DOI	10.1109/VLSIT.1998.689190
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Etching Crystallization Annealing Fabrication Capacitors Oxidation Contacts Electric variables measurement Scalability
Content Type	Text
Resource Type	Article

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