NDLI: A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

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NBTI Degradation: A Problem or a Scare?

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit

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Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware

Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors

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Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures

Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples

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Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters

Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters Design and Analysis of Critical Issues

A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation

VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair

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Energy-Efficient, High Performance Circuits for Arithmetic Units

Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters

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Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture

Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits

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Design of Reversible Finite Field Arithmetic Circuits with Error Detection

Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers

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Formal Verification of a Public-Domain DDR2 Controller Design

Enhanced TED: A New Data Structure for RTL Verification

Simulation Acceleration with HW Re-Compilation Avoidance

A Module Checking Based Converter Synthesis Approach for SoCs

Energy Reduction in SRAM using Dynamic Voltage and Frequency Management

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

Temperature and Process Variations Aware Power Gating of Functional Units

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Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Power Reduction of Functional Units Considering Temperature and Process Variations

Stall Power Reduction in Pipelined Architecture Processors

A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor

Memory Architecture Exploration Framework for Cache Based Embedded SOC

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters

A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits

GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes

Behavioral Modeling of a CMOS Compatible High Precision MEMS Based Electron Tunneling Accelerometer

An Optical Reconfiguration System with Four Contexts

An Acceleration and Optimization Method for Optical Reconfiguration

0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops

Variability-Tolerant Register-Transfer Level Synthesis

A Galois Field Based Logic Synthesis Approach with Testability

A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions

Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis

On the Use of Hash Tables for Efficient Analog Circuit Synthesis

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products

A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization

Self-Sleep Buffer for Distributed MTCMOS Design

Power Management of Interactive 3D Games Using Frame Structures

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm

Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design

Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier

Watermarking Video Clips with Workload Information for DVS

Throughput Efficient Parallel Implementation of SPIHT Algorithm

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Industry Standards from Accellera

IEEE Market-Oriented Standards Process and the EDA Industry

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A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

Content Provider	IEEE Xplore Digital Library
Author	Biswas, A.K. Hasan, M.M. Hasan, M. Chowdhury, A.R. Babu, H.M.H.
Copyright Year	2008
Description	Author affiliation: Univ. of Dhaka, Dhaka (Biswas, A.K.; Hasan, M.M.; Hasan, M.; Chowdhury, A.R.; Babu, H.M.H.)
Abstract	Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage output and delay.
Starting Page	566
Ending Page	571
File Size	759076
Page Count	6
File Format	PDF
ISBN	0769530834
ISSN	10639667
DOI	10.1109/VLSI.2008.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Delay Optical computing DH-HEMTs CMOS logic circuits Logic circuits Energy loss Physics computing Temperature Quantum computing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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