NDLI: An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application

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2015 Symposium on VLSI Circuits (VLSI Circuits)

2014 Symposium on VLSI Circuits Digest of Technical Papers

2013 Symposium on VLSI Circuits

Foreword: Welcome to the 2013 Symposium on VLSI Circuits

Executive committees

Table of contents

2013 Symposium on VLSI technology & circuits - conference schedule

Session quick index

A 9b, 1.12ps resolution 2.5b/stage pipelined time-to-digital converter in 65nm CMOS using time-register

A $0.11mm^{2},$ 5.7-to-6.7GHz, parametrically pumped quadrature LC-VCO with digital outputs

A 720µW 873MHz–1.008GHz injection-locked frequency multiplier with 0.3V supply voltage in 90nm CMOS

93% power reduction by automatic self power gating (ASPG) and multistage inverter for negative resistance (MINR) in 0.7V, 9.2µW, 39MHz crystal oscillator

A 0.9V low-power 0.4–6GHz linear SDR receiver in 28nm CMOS

An ultra low power, reconfigurable, multi-standard transceiver using fully digital PLL

Intermittent transmitter circuit with novel feedback source follower amplifier for solar powered 5-mm-cubic wireless sensor nodes with 1/20 λ dipole antenna

A −90dBm sensitivity wireless transceiver using VCO-PA-LNA-switch-modulator co-design for low power insect-based wireless sensor networks

A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

A 1.3-mW, 1.6-GHz digital delay-locked loop with two-cycle locking time and dither-free tracking

A 288fs RMS jitter versatile 8–12.4GHz wide-band Fractional-N synthesizer for SONET and SerDes communication standards in 40nm CMOS

A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter

A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

High-gain wide-bandwidth capacitor-less low-dropout regulator with zero insertion utilizing frequency response of inner loops

A pseudo-noise coded constant-off-time (PNC-COT) control switching converter with maximum 18.7 dBm peak spur reduction and 92% efficiency in 40 nm CMOS

A 10V fully-integrated bidirectional SC ladder converter in 0.13µm CMOS using nested-bootstrapped switch cells

A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS

A 100,000 fps vision sensor with embedded 535GOPS/W 256×256 SIMD processor array

A 125,582 vector/s throughput and 95.1% accuracy ANN searching processor with Neuro-Fuzzy Vision Cache for real-time object recognition

A 240×180 10mW 12us latency sparse-output vision sensor for mobile applications

A 1062Mpixels/s 8192×4320p High Efficiency Video Coding (H.265) encoder chip

An 8.5 mW, 0.07 $mm^{2}$ ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter

A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

A 25GHz 100ns lock time digital LC PLL with an 8-phase output clock

A 28GHz hybrid PLL in 32nm SOI CMOS

A MCU platform with embedded FRAM achieving 350nA current consumption in real-time clock mode with full state retention and 6.5µs system wakeup time

A 0.6V 8 pJ/write non-volatile CBRAM macro embedded in a body sensor node for ultra low energy applications

A 38% access time improvement in 40nm CMOS technology with Triple-Wire-Program-Cell scheme for high density MROM

A 28nm ROM with Two-Step Decoding scheme and OD-space-effect minimization to achieve 30% speed and 190mV Vmin improvement

A fully self-powered hybrid system based on CMOS ICs and large-area electronics for large-scale strain monitoring

A +0.4°C accurate high-speed remote junction temperature sensor with digital Beta correction and series-resistance cancellation in 65nm CMOS

A 70dB SNR capacitive touch screen panel readout IC using capacitor-less trans-impedance amplifier and coded Orthogonal Frequency-Division Multiple Sensing scheme

An integrated pulse wave velocity sensor using Bio-impedance and noise-shaped body channel communication

Integrated CMOS quantitative polymerase chain reaction lab-on-chip

An RF energy harvester with 35.7% PCE at P of −15 dBm

A self-calibrating RF energy harvester generating 1V at −26.3 dBm

A ripple voltage sensing MPPT circuit for ultra-low power microsystems

A 6.0-W bi-directional DC-DC converter for wireless power transceiver in 0.35-µm BCDMOS

A stackable, 6-cell, Li-ion, battery management IC for electric vehicles with 13, 12-bit ΣΔ ADCs, cell balancing, and direct-connect current-mode communications

A 12Gb/s 0.92mW/Gb/s forwarded clock receiver based on ILO with 60MHz jitter tracking bandwidth variation using duty cycle adjuster in 65nm CMOS

An 8-to-16GHz 28nm CMOS clock distribution circuit based on mutual-injection-locked ring oscillators

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM

A 400MHz – 1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface

A self-powered CMOS reconfigurable multi-sensor SoC for biomedical applications

A low-power microprocessor for data-driven analysis of analytically-intractable physiological signals in advanced medical sensors

A 48.6-to-105.2µW machine-learning assisted cardiac sensor SoC for mobile healthcare monitoring

A 0.36V, 33.3µW 18-band ANSI S1.11 1/3-octave filter bank for digital hearing aids in 40nm CMOS

A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation

A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS

A 13-Bit 9GS/s RF DAC-based broadband transmitter in 28nm CMOS

An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI

A $0.0058mm^{2}$ 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique

A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS

A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS

A 6b 10GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS

A 2.8 mW/Gb/s quad-channel 8.5–11.4 Gb/s quasi-digital transceiver in 28 nm CMOS

A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR

A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering

A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS

A 1.59Gpixel/s motion estimation processor with −211-to-211 search range for UHDTV video encoder

A 96.5% energy-reduced lookup engine with an unused-rules-exception scheme for greening networks

Shortstop: An on-chip fast supply boosting technique

A Fully-Integrated 77GHz phase-array radar system with 1TX/4RX frontend and digital beamforming technique

A 4-element 60-GHz CMOS phased-array receiver with transformer-based hybrid-mode mixing and closed-loop beam-forming calibration

160GHz pulsed transmitter with packaged antenna array in 65nm CMOS

A low-power 60-GHz CMOS transceiver for WiGig applications

A 1-inch optical format, 14.2M-pixel, 80fps CMOS image sensor with a pipelined pixel reset and readout operation

A 5.9µm-pixel 2D/3D image sensor with background suppression over 100klx

An ultra-low noise photoconductive film image sensor with a high-speed column feedback amplifier noise canceller

A 100-fps fluorescence lifetime imager in standard 0.13-µm CMOS

820-GHz imaging array using diode-connected NMOS transistors in 130-nm CMOS

An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application

3D IC heterogeneous integration of GPS RF receiver, baseband, and DRAM on CoWoS with system BIST solution

3D stackable vertical-gate BE-SONOS NAND flash with layer-aware program-and-read schemes and wave-propagation fail-bit-detection against cross-layer process variations

A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC

Scalable 3D-FPGA using wafer-to-wafer TSV interconnect of 15 Tbps/W, 3.3 $Tbps/mm^{2}$

A 200-channel 10µW $0.04mm^{2}$ dual-mode acquisition IC for high density MEA

A neurochemical pattern generator SoC with switched-electrode management for single-chip electrical stimulation and 9.3µW, 78pA, 400V/s FSCV sensing

A 28.6µW mixed-signal processor for epileptic seizure detection

A 1024-channel CMOS microelectrode-array system with 26'400 electrodes for recording and stimulation of electro-active cells in-vitro

A 51fA/Hz0.5 low power heterodyne impedance analyzer for electrochemical impedance spectroscopy

A 75.1dB SNDR 840MS/s CT ΔΣ modulator with 30MHz bandwidth and 46.4fJ/conv FOM in 55nm CMOS

A 69dB SNDR, 25MHz BW, 800MS/s continuous-time bandpass ΔΣ ADC using DAC duty cycle control for low power and reconfigurability

A 66dB SNDR 15MHz BW SAR assisted ΔΣ ADC in 22nm tri-gate CMOS

A 379nW 58.5dB SNDR VCO-based ΔΣ modulator for bio-potential monitoring

A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS

A 2dB NF receiver with 10mA battery current suitable for coexistence applications

A low-cost SAW-less GSM/GPRS SoC with integrated connectivity and 32-kHz crystal removal in 55nm

A 1.15V low power mobile ISDB-Tsb/Tmm/T and DVB-T tuner SoC in 40nm CMOS

Two-channel receiver back-end using statistically calibrated HRM with >70dB $3^{rd}$ and $5^{th}$ harmonic rejection for carrier aggregation in 32nm CMOS

Perspectives on mobile devices and their impact on semiconductor technologies

Glass for the future: Displays and semiconductors

A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS

A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC

A 70MS/s 69.3dB SNDR 38.2fJ/conversion-step time-based pipelined ADC

A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end

A 10-Bit 800-MHz 19-mW CMOS ADC

1Mb 0.41 $µm^{2}$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing

Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine

A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) Cell and read-disturb-free temperature-aware current-mode read scheme

Enabling circuit design using FinFETs through close ecosystem collaboration

A 3.6GB/s 1.3mW 400mV $0.051mm^{2}$ near-threshold voltage resilient router in 22nm tri-gate CMOS

Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance

Process and local layout effect interaction on a high performance planar 20nm CMOS

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Design for ESD protection at its limits

Application of low-noise TIA ICs for novel sensing of MOSFET noise up to the GHz region

First demonstration of a full 28nm high-k/metal gate circuit transfer from Bulk to UTBB FDSOI technology through hybrid integration

2.6GHz ultra-wide voltage range energy efficient dual A9 in 28nm UTBB FD-SOI

Fully-depleted planar technologies and static RAM

A 20nm 0.6V 2.1µW/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme

FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias

Enhancing SRAM performance by advanced FinFET device and circuit technology collaboration for 14nm node and beyond

Dual-VCC 8T-bitcell SRAM Array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency

A 22nm 2.5MB slice on-die L3 cache for the next generation $Xeon^{®}$ Processor

A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB

High-performance Si channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions

First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects

Thin organic photoconductive film image sensors with extremely high saturation of 8500 $electrons/µm^{2}$

2012 Symposium on VLSI Circuits (VLSIC)

2011 Symposium on VLSI Circuits - Digest of Technical Papers

2010 Symposium on VLSI Circuits

2009 Symposium on VLSI Circuits

2008 IEEE Symposium on VLSI Circuits

2007 IEEE Symposium on VLSI Circuits

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

Symposium 1997 on VLSI Circuits

1996 Symposium on VLSI Circuits. Digest of Technical Papers

Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Symposium 1993 on VLSI Circuits

1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Symposium 1989 on VLSI Circuits

Symposium 1988 on VLSI Circuits

An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application

Content Provider	IEEE Xplore Digital Library
Author	Mu-Shan Lin Chien-Chun Tsai Chih-Hsien Chang Wen-Hung Huang Ying-Yu Hsu Shu-Chun Yang Chin-Ming Fu Mao-Hsuan Chou Tien-Chien Huang Ching-Fang Chen Tze-Chiang Huang Adham, S. Min-Jer Wang Shen, W.W. Mehta, A.
Copyright Year	2013
Description	Author affiliation: HSCD/DTP, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan (Mu-Shan Lin; Chien-Chun Tsai; Chih-Hsien Chang; Wen-Hung Huang; Ying-Yu Hsu; Shu-Chun Yang; Chin-Ming Fu; Mao-Hsuan Chou; Tien-Chien Huang; Ching-Fang Chen; Tze-Chiang Huang; Adham, S.; Min-Jer Wang; Shen, W.W.; Mehta, A.) A 1Tbit/s bandwidth PHY is demonstrated through 2.5D CoWoS platform. Two chips: SOC and eDRAM have been fabricated in TSMC 40nm CMOS technology and stacked on another silicon interposer chip in 65nm technology. Total 1024 DQ bus operating in 1.1Gbit/s with Vmin=0.3V are proven in experimental results. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY that excludes PLL/DLL but retains good timing margin. Another data sampling alignment training approach is reserved to enhance timing robustness. A compact low-swing IO also achieves great power efficiency of 0.105mW/Gbps.
Sponsorship	IEEE Electron Devices Soc.
File Size	1589929
File Format	PDF
ISBN	9781467355315
e-ISBN	9784863483484
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Clocks Timing Phase locked loops System-on-chip Training Stacking Silicon
Content Type	Text
Resource Type	Article

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