NDLI: A 286 MHz 64-bit floating point multiplier with enhanced CG operation

Content Provider	IEEE Xplore Digital Library
Author	Makino, H. Suzuki, H. Morinaka, H. Nakase, Y. Mashiko, K.
Copyright Year	1995
Description	Author affiliation: LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Itami, Japan (Makino, H.; Suzuki, H.; Morinaka, H.; Nakase, Y.; Mashiko, K.)
Abstract	High speed floating point (FP) multipliers are essential for high speed calculation systems because increasingly large numbers of FP multiplications must be carried out in various applications such as scientific calculation and computer graphics (CG). CG, in particular, requires enormous amount of FP multiplications to obtain high quality images required for multimedia systems. To realize high speed, the critical path delay must be minimized. In this paper, we discuss a method to shorten the delay time of the critical path. Then we present an FP multiplier design based on the method. A special function for CG is also implemented without increasing the critical path delay. Finally, we show the fabrication and test results of the FP multiplier.
Starting Page	15
Ending Page	16
File Size	329353
Page Count	2
File Format	PDF
ISBN	0780025990
DOI	10.1109/VLSIC.1995.520666
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-06-08
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Character generation CMOS logic circuits Circuit simulation Delay effects Logic gates Degradation Large scale integration Laboratories Application software Computer graphics
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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