NDLI: Overcoming the limitations of self-checking stimulus through the use of an ASIC mirror

Content Provider	IEEE Xplore Digital Library
Author	Benson, R.D.
Copyright Year	1998
Description	Author affiliation: Syst. Simulation Corp., Compaq Comput. Corp., Houston, TX, USA (Benson, R.D.)
Abstract	One of the greatest challenges of verification is the handling of concurrency in a system. A good example of this concurrency is the CPU-to-memory bridge within a desktop PC. The bridge ASIC connects the CPU bus with three different expansion busses, and it allows concurrent accesses from bus-masters on those busses to main memory. This paper describes a tool that was written as part of the verification project for just such an ASIC. This tool, called an ASIC mirror, provided cycle-for-cycle coherency checks for cycles and data for the CPU bus and all of the expansion busses connected to the bridge ASIC. Many of the checks provided by the ASIC mirror would have been virtually impossible to carry out by the use of self-checking stimulus alone. The architecture of the ASIC mirror and some examples of the bugs in the ASIC that were found by the mirror are discussed in this paper.
Starting Page	148
Ending Page	152
File Size	35834
Page Count	5
File Format	PDF
ISBN	0818684151
ISSN	10859403
DOI	10.1109/IVC.1998.660694
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Mirrors Bridges SDRAM Master-slave Computational modeling Computer simulation System testing Concurrent computing Read only memory
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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