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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Olmos, J.J. Agusti, R. |
| Copyright Year | 1992 |
| Description | Author affiliation: Dept. de Teoria del Senyal i Comunicacions, Univ. Politecnica de Catalunya, Barcelona, Spain (Olmos, J.J.; Agusti, R.) |
| Abstract | In code-division multiple access (CDMA) systems a delay-lock loop (DLL) is used to keep a fine alignment between sequences. A simulation program for the second-order DLL has been developed. The program allows an optimum design of the loop low-pass filter in order to guarantee the right clock frequency acquisition and minimum residual jitter. The mean time to lose lock (MTLL) of the DLL has also been obtained by computer simulation for two different shifts between early and late codes. Results show a remarkable sensitivity to the signal-to-noise-ratio in the data bandwidth. |
| Starting Page | 221 |
| Ending Page | 224 |
| File Size | 271111 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780306732 |
| ISSN | 10903038 |
| DOI | 10.1109/VETEC.1992.245436 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1992-05-10 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Multiaccess communication Delay systems Computational modeling Low pass filters Clocks Frequency Jitter Computer simulation Signal to noise ratio Bandwidth |
| Content Type | Text |
| Resource Type | Article |
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