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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cavers, J.K. |
| Copyright Year | 1987 |
| Description | Author affiliation: Simon Fraser University, Burnaby, B.C., Canada (Cavers, J.K.) |
| Abstract | The few published descriptions of bit timing recovery for GTFM or GMSK adopt the traditional analog approaches developed for MSK: typically, a collection of nonlinearities, filters, mixers and dividers. The result in a hardware implementation is an increase in parts count and cost. In a software implementation (i.e. on a signal processor) it is prohibitive, since the extra computation is magnified many times by the requirement for several samples per bit. This paper describes a good synchronizer which requires only the same once-per-bit samples used to make bit decisions, adding a negligible additional computation or hardware load. Analysis for high SNR highlights an explicit tradeoff among crystal accuracy, timing jitter and SNR. Simulation results demonstrate performance which is virtually identical to more complex methods. At the time of writing, the method, or a minor variant, has been implemented successfully in three different prototype modems. |
| Starting Page | 266 |
| Ending Page | 271 |
| File Size | 435642 |
| Page Count | 6 |
| File Format | |
| DOI | 10.1109/VTC.1987.1623555 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1987-06-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Filters Costs Signal processing Accuracy Timing jitter Computational modeling Writing Prototypes Modems |
| Content Type | Text |
| Resource Type | Article |
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